Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.

A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.

An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole. A contact plug extends through the contact hole in the interlayered dielectric layer, and an upper interconnection line extends in the trench of the interlayered dielectric layer and connects to the contact plug. The contact plug includes lower and upper sidewalls inclined at first and second angles, respectively, relative to the underlying layer, and the second angle is less than the first angle. Related devices and fabrication methods are also discussed.

A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.

An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole. A contact plug extends through the contact hole in the interlayered dielectric layer, and an upper interconnection line extends in the trench of the interlayered dielectric layer and connects to the contact plug. The contact plug includes lower and upper sidewalls inclined at first and second angles, respectively, relative to the underlying layer, and the second angle is less than the first angle. Related devices and fabrication methods are also discussed.

A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.

A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.

Embodiments are disclosed for processing microelectronic workpieces having patterned structures that include ultra-low dielectric constant (k) (ULK) material layers. In particular, embodiments are disclosed that deposit protective layers to protect ULK features during etch processing of patterned structures within substrates for microelectronic workpieces. For certain embodiments, these protective layers are deposited in-situ within the etch chamber.