A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between a portion of the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different. The air gaps are located between another portion of the dielectric layer and the second conductive layer.

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.