A process for manufacturing interconnect BEOL structures from a patternable low-k dielectric on a microcircuit substrate having an optional anti-reflective coating comprises applying to the microcircuit substrate a via coating for forming a via comprising a low-k patternable dielectric coating, exposing the via coating to a via pattern, developing the exposed via coating, curing the exposed and developed via coating to form a via film, applying a trench coating for forming a trench comprising a patternable low-k dielectric coating, exposing the trench coating to a trench pattern, developing the exposed and developed trench coating, followed by curing the trench coating to form a trench film; Curing one of the uncured coatings to form a film prevents it from inter-mixing with the other applied uncured coating. Articles of manufacture comprise products made by this process as well as dual-damascene integrated spun-on patterned low-k dielectrics, and single-damascene integrated spun-on patterned low-k dielectrics.

A semiconductor device comprises conductive lines, a conductive landing pad in electrical communication with a conductive line of the conductive lines, and a conductive interconnect structure in electrical communication with the conductive landing pad. The conductive interconnect structure comprises a contact plug in electrical communication with the conductive landing pad, and a global interconnect contact in electrical communication with the contact plug and having a greater lateral width than the contact plug. Related electronic systems and method are also disclosed.

A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

Methods of depositing a carbon film are discussed. Some embodiments selectively deposit a carbon film on a metal surface over a dielectric surface. Some embodiments form carbon pillars on metal surfaces selectively over dielectric surfaces. Some embodiments utilize carbon pillars in forming self-aligned vias.

A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by an exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.

A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.