Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.

A method for fabricating a semiconductor device includes: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.

A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.

An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized dielectric surface layer within the interconnect dielectric material. A metal layer is formed on the nitridized dielectric surface layer and then an anneal is performed to form a metal nitride layer between the metal layer and the nitridized dielectric surface layer. A portion of the originally deposited metal layer that is not reacted with the nitridized dielectric surface is then selectively removed and thereafter an electrical conducting structure is formed directly on the metal nitride layer that is present in the opening.

An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.

Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.

One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.