A semiconductor device includes a substrate, a first interlayer insulating layer on the substrate, a lower wiring pattern inside the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer, a second interlayer insulating layer on the etch stop layer, a via trench inside the second interlayer insulating layer and the etch stop layer and that extends to the lower wiring pattern, a via inside the via trench and that is in contact with the second interlayer insulating layer and is formed of a single film, an upper wiring trench formed inside the second interlayer insulating layer on the via, and an upper wiring pattern inside the upper wiring trench and that includes an upper wiring barrier layer and an upper wiring filling layer on the upper wiring barrier layer An upper surface of the via is in contact with the upper wiring filling layer.

A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.

Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.