Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.

A semiconductor structure and a formation method thereof are provided. A form of the formation method of the semiconductor structure includes: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; forming a seed layer on a bottom and a sidewall of the contact hole, where a thickness of the seed layer on the bottom of the contact hole is greater than a thickness of the seed layer on the sidewall of the contact hole; and forming a conductive plug in the contact hole. The semiconductor structure includes: a substrate; a dielectric layer located on the substrate; a contact hole located in the dielectric layer; a seed layer located on a bottom and a sidewall of the contact hole, where a thickness of the seed layer on the bottom of the contact hole is greater than a thickness of the seed layer on the sidewall of the contact hole; and a conductive plug located in the contact hole. The present disclosure can improve the reliability of an electrical connection of the conductive plug.

An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.

Methods for forming a copper seed layer having improved anti-migration properties are described herein. In one embodiment, a method includes forming a first copper layer in a feature, forming a ruthenium layer over the first copper layer in the feature, and forming a second copper layer on the ruthenium layer in the feature. The ruthenium layer substantially locks the copper layer there below in place in the feature, preventing substantial physical migration thereof.

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.

A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor layer sequence having an active region configured to emit radiation, a dielectric layer, a solder layer including a first metal arranged on the dielectric layer and a seed layer arranged between the solder layer and the dielectric layer, wherein the seed layer includes the first metal and a second metal, wherein the second metal is less noble than the first metal, wherein an amount of the second metal in the seed layer is between 0.5 wt % and 10 wt %, and wherein the first metal is Au and the second metal is Zn.

A method which exploits the benefits of a seed enhancement layer (in terms of void-free copper fill), while preventing copper volume loss during planarization, is provided. The method includes forming a partial seed enhancement liner in a lower portion of an opening that contains a recessed copper portion. Additional copper is formed in the upper portion of the opening providing a copper structure in which no copper volume loss at the uppermost interface of the copper structure is observed.