Generally discussed herein are systems, devices, and methods that include a communication cavity. According to an example a device can include substrate with a first cavity formed therein, first and second antennas exposed in and enclosed by the cavity, and an interconnect structure formed in the substrate, the interconnect structure including alternating conductive material layers and inter-layer dielectric layers.

The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

An integrated circuit (IC) comprises a substrate, a first die mounted on the substrate, a second die mounted on the substrate and a waveguide structure mounted on the first die and the second die to enable high frequency wireless communication between the first die and the second die.

An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are at a point of rapid growth in defense (radar, SATCOM) and commercial (5G and beyond) industries. This growth also comes at a point at which the standard GaN heterostructures remain unoptimized for maximum performance. For this reason, the shift to the aluminum nitride (AlN) platform is disclosed. AlN allows for smarter, highly-scaled heterostructure design that improves the output power and thermal management of GaN amplifiers. Beyond improvements over the incumbent amplifier technology, AlN allows for a level of integration previously unachievable with GaN electronics. State-of-the-art high-current p-channel FETs, mature filter technology, and advanced waveguides, all monolithically integrated with an AlN/GaN/AlN HEMT, is made possible with aluminum nitride. It is on this AlN platform that nitride electronics may maximize their full high-power, highspeed potential for mm-wave communication and high-power logic applications.