A flat panel substrate with integrated antennas and wireless power transmission system for delivering power to a receiving device is presented herein. A method can comprise depositing, onto a flat panel substrate, an antenna layer comprising multiple adaptively phased antennas elements; and depositing, onto the flat panel substrate, respective thin film transistor (TFT)-based antenna management circuits for the multiple adaptively phased antenna elements—the respective TFT-based antenna management circuits being operable to measure respective first phases at which first signals are received at the multiple adaptively phased antenna elements, and based on the respective first phases, control respective second phases at which second signals are transmitted from the multiple adaptively phased antenna elements to facilitate delivery, via the second signals, of power to the receiving device. Further, the method comprises forming traces communicatively coupling the multiple adaptively phased antenna elements to the respective TFT-based antenna management circuits.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

Density-graded adhesion layers on conductive structures within a microelectronic package substrate are described. An example is a density-graded adhesion layer that includes a dense region proximate to a conductive structure that is surrounded by a less dense (or porous) region adjacent to an overlying dielectric layer. Providing such a graded adhesion layer can have a number of benefits, which can include providing both mechanical connections for improved adhesion with a surrounding dielectric layer and provide hermetic protection for the underlying conductive structure from corrosive species. The adhesion layer enables the conductive structure to maintain its as-formed smooth surface which in turn reduces insertion loss of signals transmitted through the conductive structure.

A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.

A semiconductor package includes a substrate, an interposer, a primary component layer, a first redistribution layer, multiple solder bumps and a first hybrid bonding structure. The interposer is disposed above the substrate and includes multiple TSV sets. The primary component layer is disposed above the interposer and includes multiple first chips and a first molding material that fills the space between the multiple first chips. The first redistribution layer is disposed between the primary component layer and the interposer and includes at least one portion of an antenna structure. The plurality of solder bumps is disposed between the substrate and the interposer. The first hybrid bonding structure is disposed between the multiple first chips and the multiple TSV sets for electrical connection in between and includes multiple connection components that respectively apply bonding of multiple metal pieces in between.

A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate.

A microelectronics package assembly and process of making same are disclosed. The flange has an upper surface and a first coating disposed on the upper surface of the flange. The insulator has a bottom surface for mounting onto the flange and an upper surface opposite the bottom surface. A second coating is disposed on the bottom surface of the insulator and a third coating disposed on the upper surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of less than or equal to 1 micron. At least one of the first coating, the second coating, and the third coating is applied via at least one of physical vapor deposition, atomic deposition, or chemical deposition.

An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.

There is provided an active phased array antenna in which power to an Si wafer is separated from power to compound semiconductor chips. An active phased array antenna is an active phased array antenna including a substrate having a plurality of antenna elements; a pseudo wafer containing a group of semiconductor chips including a plurality of semiconductor chips made of compound semiconductors; and a silicon wafer made of silicon, the substrate, the pseudo wafer, and the silicon wafer being stacked on top of each other in this order, and the pseudo wafer includes first feeders for supplying power to the group of semiconductor chips from the substrate; and a second feeder for supplying power to the silicon wafer from the substrate, the second feeder passing through the pseudo wafer in a thickness direction of the pseudo wafer.