The present invention relates to a two-end driving, high-frequency sub-substrate structure, comprising a sub-substrate body, wherein: the sub-substrate body has an upper side provided with a first signal pad area and a second signal pad area, the first signal pad area and the second signal pad area are symmetric with respect to each other, each of the first signal pad area and the second signal pad area extends from one of two lateral portions of the sub-substrate body in an extending direction toward a center of the sub-substrate body and terminates in an end, the end of the first signal pad area is adjacent to but spaced from the end of the second signal pad area, the first signal pad area is configured for supporting a semiconductor chip provided thereon, the second signal pad area is provided with a jumper wire connected to an electrode of the semiconductor chip, there are two grounding pad areas provided respectively on two lateral sides of the first signal pad area and the second signal pad area and constituting a portion of a coplanar waveguide, the sub-substrate body has an inner layer or bottom side that is provided with a grounding layer or combined with a grounding layer.

A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.

Provided is an integrated antenna package structure including a chip, a circuit structure, a shielding body, an encapsulant, a first antenna layer, a dielectric body, and a second antenna layer. The circuit structure is electrically connected to the chip. The shielding body is disposed on the circuit structure and has an accommodating space. The chip is disposed in the accommodating space of the shielding body. The encapsulant is disposed on the circuit structure and covers the chip. The first antenna layer is disposed on the circuit structure and is electrically connected to the circuit structure. The dielectric body is disposed on the encapsulant. The second antenna layer is disposed on the dielectric body. A manufacturing method of the integrated antenna package structure is also provided.

An apparatus is described. The apparatus includes a semiconductor chip package substrate having a transmission line. The transmission line has a conductor to conduct current of a signal that is propagated along the transmission line. The conductor has an expanding width as the conductor approaches a vertical transition region. The vertical transition region is between the conductor and a solder ball. The transition region has multiple conducting vias at a same layer of the substrate. The multiple conducting vias are electrically connected to the conductor. The multiple conducting vias are radially arranged around a center axis of the solder ball.

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

Packaged modules for use in wireless devices are disclosed. A substrate supports integrated circuit die including at least a portion of a baseband system and a front end system, an oscillator assembly, and an antenna. The oscillator assembly includes an enclosure to enclose the oscillator and conductive pillars formed at least partially within a side of the enclosure to conduct signals between the top and bottom surfaces of the oscillator assembly. Components can be vertically integrated to save space and reduce trace length. Vertical integration provides an overhang volume that can include discrete components. Radio frequency shielding and ground planes within the substrate shield the front end system and antenna from radio frequency interference. Stacked filter assemblies include passive surface mount devices to filter radio frequency signals.

A method of forming a semiconductor structure is provided. A first inter-level dielectric (ILD) layer is formed overlying a molding layer. The first ILD layer is patterned to form a plurality of first openings. A first lower transmitter electrode and a first lower receiver electrode are formed by depositing a first metal material within the plurality of first openings. A first dielectric waveguide is formed overlying the first ILD layer, the first lower transmitter electrode and the first lower receiver electrode. A second ILD layer is formed overlying the first dielectric waveguide and includes a plurality of second openings. A second lower transmitter electrode and a second lower receiver electrode are formed by depositing a second metal material within the plurality of second openings. A second dielectric waveguide is formed overlying the second ILD layer, the second lower transmitter electrode and the second lower receiver electrode.

The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.

A flat panel substrate with integrated antennas and wireless power transmission system for delivering power to a receiving device is presented herein. A method can comprise depositing, onto a flat panel substrate, an antenna layer comprising multiple adaptively phased antennas elements; and depositing, onto the flat panel substrate, respective thin film transistor (TFT)-based antenna management circuits for the multiple adaptively phased antenna elements—the respective TFT-based antenna management circuits being operable to measure respective first phases at which first signals are received at the multiple adaptively phased antenna elements, and based on the respective first phases, control respective second phases at which second signals are transmitted from the multiple adaptively phased antenna elements to facilitate delivery, via the second signals, of power to the receiving device. Further, the method comprises forming traces communicatively coupling the multiple adaptively phased antenna elements to the respective TFT-based antenna management circuits.