Disclosed in an electronic device, which includes a housing that includes a first plate and a second plate facing a direction opposite the first plate, a conductive plate that is disposed in a first plane between the first plate and the second plate, and is parallel to the second plate, a wireless communication circuit that is disposed within the housing and is configured to transmit and/or receive a signal having a frequency ranging from 20 GHz to 100 GHz, a first electrical path having a first end electrically connected with the wireless communication circuit and a second end floated, the first electrical path including a first portion between the first end and the second end, a second electrical path having a third end electrically connected with the conductive plate and a fourth end floated, the second electrical path including a second portion between the third end and the fourth end.

A method of forming a semiconductor structure is provided. A first inter-level dielectric (ILD) layer is formed overlying a molding layer. The first ILD layer is patterned to form a plurality of first openings. A first lower transmitter electrode and a first lower receiver electrode are formed by depositing a first metal material within the plurality of first openings. A first dielectric waveguide is formed overlying the first ILD layer, the first lower transmitter electrode and the first lower receiver electrode. A second ILD layer is formed overlying the first dielectric waveguide and includes a plurality of second openings. A second lower transmitter electrode and a second lower receiver electrode are formed by depositing a second metal material within the plurality of second openings. A second dielectric waveguide is formed overlying the second ILD layer, the second lower transmitter electrode and the second lower receiver electrode.

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

A transformer balun fabricated in silicon and including a series of alternating metal layers and dielectric layers that define first and second outer conductors that are part of a coaxial structure. Each dielectric layer includes a plurality of conductive vias extending through the dielectric layer to provide electrical contact between opposing metal layers, where a top metal layer forms a top wall of each outer conductor and a bottom metal layer forms a bottom wall of each outer conductor and the other metal layers and the dielectric layers define sidewalls of the outer conductors. Inner conductors extends down both of the first and second outer conductors and a first output line is electrically coupled to a sidewall of the first outer conductor and a second output line is electrically coupled to a sidewall of the second outer conductor.

A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.

A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

The coaxial cable assembly generally has a coaxial cable; and a connector assembled to an end of the coaxial cable, the connector having a dielectric body having a connecting surface, a longitudinal groove recessed in the connecting surface and having a groove end spaced from an edge of the connecting surface, and a coplanar waveguide along the connecting surface, the coplanar waveguide having a signal conductor extending from the groove end to the edge and between ground conductors each extending from a respective lateral side of the longitudinal groove to the edge; the end of the coaxial cable being received in the longitudinal groove and having an inner conductor electrically connected to the signal conductor and an outer conductor electrically connected to the ground conductors in a manner allowing connection of the coaxial cable with another coplanar waveguide of an integrated circuit.

Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.