A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

An apparatus may include a controller die configured to communicate with a plurality of dies via a transmission line. The controller die may be configured to transmit a signal on the transmission line to a target die of the plurality of dies, or the target die may transmit a signal on the transmission line. The transmission may be dependent on an end die of the plurality of dies setting an end-die termination resistance to a low level. In situations where the target memory is receiving the signal, the target die may set target an on-die termination resistance to a high level. In situations where the target memory die is transmitting the signal, the target die may set an on-die termination resistance to a low level.

A wave communication system includes an integrated circuit and a multilayered substrate. The multilayered substrate is electrically coupled to the integrated circuit. The multilayered substrate includes an antenna structure configured to transmit a circularly polarized wave in response to signals from the integrated circuit.

Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.

Package design method for semiconductor chip package for high speed SerDes signals for optimization of package differential impedance and reduction of package differential insertion loss and differential return loss at data rates of 25 to 60 Gb/s and beyond. The method optimizes parameters of vertical interconnections of BGA ball, via, and PTH, and around the joint between vertical and horizontal interconnections of traces. Also disclosed are examples of chip package designs for high speed SerDes signals, including one using 0.8 mm BGA ball pitch and IO-layer buildup substrate, one using 1 mm BGA ball pitch and 14-layer buildup substrate, one using 6-layer buildup substrate with signals routed on top and bottom metal layers with microstrip line structure, and one using 12-layer package substrate with unique via configuration, all of which achieve low substrate differential impedance discontinuity, reduced differential insertion loss and differential return loss between BGA balls and C4 bumps.

Techniques pertaining to designs of integrated circuits having on-chip inductors with low common mode coupling effect are described. According to one aspect of the present invention, an integrated circuit is designed to have a first circuit operating at a first frequency and including a first inductor, and a second circuit including a second inductor and provided to process an input signal. The second circuit includes a second inductor and is provided to process an input signal. The second inductor includes a first terminal, a second terminal, an intermediate terminal, and an intermediate node, wherein a first wire is formed between the first terminal and the intermediate node, a second wire is formed between the intermediate node and the second terminal, and an intermediate tap is coupled between the intermediate node and the intermediate terminal, the first wire and the second wire forming a coil with one or more turns, and the first terminal, the second terminal and the intermediate terminal of the second inductor being located on one side of the coil and adjacent to each other.

A high-voltage capacitor structure comprises a capacitor. The capacitor includes a substrate, a field oxidation layer, an active region, a dielectric layer, a passivation layer and a metal layer. The field oxidation layer is disposed above the substrate. The active region is disposed above the substrate or in the substrate. The dielectric layer is disposed above the active region and the field oxidation layer. The passivation layer is disposed above the dielectric layer. The metal layer is disposed above the passivation layer. The metal layer and the active region serve as a first electrode and a second electrode of the capacitor, respectively, wherein the active region is disposed below the dielectric layer. Some embodiments provide a digital isolation apparatus comprising at least one high-voltage isolator, each of which includes the above high-voltage capacitor structure.

In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.