The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Apparatus and methods are provided for providing provide high-speed interconnect using bond wires. According to various aspects of the subject innovation, the provided techniques may provide a ground shape to shield a high-speed signal wire from the substrate in a semiconductor assembly. In an exemplary embodiment, there is provided an assembly that may comprise a substrate, a semiconductor die attached to the substrate, a signal bond wire connecting a bond pad on the semiconductor die and a bond finger on the substrate, and a ground shape on the substrate to shield the signal wire from the substrate.

The present disclosure provides a panel, a manufacturing method for the same, and a terminal. The panel includes: a base substrate; at least one differential signal line group on the base substrate, each including two signal lines; and at least one ground wire group on the base substrate and on the same side of the base substrate as the at least one differential signal line group. The at least one ground wire group is in one-to-one correspondence with the at least one differential signal line group, each ground wire group includes two ground wires, and orthographic projections of the two ground wires in each ground wire group on the base substrate are on two sides of an orthographic projection of a corresponding differential signal line group on the base substrate, respectively.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

An integrated circuit (IC) package is described. The IC package includes back-end-of-line layers on a substrate. The IC package also includes a nested interconnect structure on the back-end-of-line layers on the substrate. The nested interconnect structure is composed of an inner core pad and an outer ring pad in a concentric arrangement. The IC package further includes a redistribution layer on the nested interconnect structure. The IC package also includes an under bump metallization layer on the redistribution layer to support package balls.

An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit. Also, one-data-width distance is obtained by converting one-data-width interval, which is corresponding to a sampling period of an equalizer provided in one of the transmission unit and the receiving unit, to a distance. Further, a first reflection source for reflecting the signal is arranged at a position of the transmission line portion, where is corresponding to a ½-data-width distance corresponding to a half of the one-data-width distance. Here, the position corresponds to a grid point where a row grid line drawn on a screen used in the designing method and a column grid line drawn on the screen intersect with each other.

A packaged integrated circuit (IC) includes an IC die having first and second external contacts and a package substrate. The IC die is attached to the package substrate which includes a balun in a first metal layer. The balun is connected to the first and second external contacts of the IC die and to a first external contact of the package substrate. The first and second external contacts of the IC die communicate a differential signal with the package substrate, and the first external contact of the package substrate communicates a single-ended signal corresponding to the differential signal. Alternatively, the balun is connected to an external contact of the IC die and to first and second external contacts of the package substrate, in which the external contact of the IC die communicates a single-ended signal and the first and second external contacts of the package substrate communicate a differential signal.