A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.

A semiconductor device includes a receiving terminal for receiving a signal transmitted through a signal transmission line, a reference plane voltage terminal connected to a refence plane as a refence for the signal on the signal transmission line and a voltage generating circuit configured to generate a refence plane voltage to be supplied to the reference plane voltage terminal based on the signal received by the receiving terminal.

An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

A functional panel, a method of manufacturing the same, and a terminal are disclosed. The functional panel includes a base substrate, at least one differential signal line group on the base substrate, where each differential signal line group of the at least one differential signal line group includes two signal lines and at least one ground line group on the base substrate and on the same side of the base substrate as the at least one differential signal line group. Each ground line group of the at least one ground line group includes two ground lines. Each ground line group corresponds to each differential signal line group one-to-one, and orthographic projections of the two ground lines in each ground line group on the base substrate are on both sides of an orthographic projection of a corresponding differential signal line group on the base substrate, and two ground lines in the ground line group are connected to a same reference ground.

Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

In accordance with embodiments disclosed herein, there is provided a high-density dual-embedded-microstrip interconnect. An interconnect includes a reference layer and a dielectric disposed on the reference layer. The interconnect further includes a pair of conductors including a first conductor and a second conductor that are in an edge-facing orientation. The interconnect further includes a third conductor. The pair of conductors may be disposed within the dielectric and the third conductor may be disposed on the dielectric above the pair of conductors. The pair of conductors may be disposed on the dielectric and the third conductor may be disposed within the dielectric below the pair of conductors. First noise received by the third conductor from the first conductor and second noise received by the third conductor from the second conductor at least partially cancel out.

A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

A memory card includes a memory card body dimensioned to house at least one integrated circuit die package. The memory card body, in certain embodiments, includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card also includes a contact pad disposed on at least one side surface of the plurality of side surfaces. The contact pad includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.