Improved power amplifier (PA) bias circuit having parallel emitter follower. In some embodiments, a bias circuit for a PA can include a first bias path implemented to couple a base node of an amplifying transistor and a supply node, with the first bias path being configured to provide a base bias current to the base node. The PA can further include a second bias path implemented to be electrically parallel with the first bias path between the base node and the supply node. The second bias path can be configured to provide an additional base bias current to the base node under a selected condition.

A transmission circuit includes a driver circuit that includes: a transistor to regulate output impedance, and a switching circuit that is connected to the transistor to regulate output impedance and switches an output polarity for differential output; and a bias circuit that includes: a first replica circuit including another transistor corresponding to the transistor to regulate output impedance, the bias circuit generating a gate voltage so as to make a current-voltage characteristic of the transistor to regulate output impedance correspond to a first output impedance value, and supply the gate voltage to a gate of the transistor to regulate output impedance.

An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.

Example embodiments relate to compact Doherty amplifiers having improved video bandwidth. One example embodiment includes an amplifier. The amplifier includes a package having a substrate. The amplifier also includes at least one amplifier unit arranged in the package. Each amplifier unit includes an input terminal and an output terminal. Each amplifier unit also includes an active semiconductor die on which a high-power transistor is integrated. Additionally, each amplifier unit includes an input matching capacitor and an output matching capacitor. Further, each amplifier unit includes a third inductor connecting an output of the high-power transistor to the output matching capacitor. In addition, each amplifier unit includes a fourth inductor connecting an input of the high-power transistor to the input matching capacitor. Yet further, each amplifier unit includes an output resonance network including a series connection of a first inductor and a first capacitor. Each amplifier unit includes a passive semiconductor die.

A semiconductor device includes a substrate, a channel layer provided on the substrate, a semiconductor layer provided on the channel layer, gate fingers and a gate connection wiring provided on the semiconductor layer, and an insulating film provided between the semiconductor layer and the gate fingers, wherein the gate fingers includes a first gate finger, and a second gate finger closer to the center of the gate fingers in an arrangement direction than the first gate finger, wherein a first distance between a lower surface of the first gate finger in contact with the insulating film and an upper surface of the channel layer in contact with the semiconductor layer is greater than a second distance between a lower surface of the second gate finger in contact with the insulating film and the upper surface of the channel layer in contact with the semiconductor layer.

Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.

Linearizing circuit and method for amplifier. In some embodiments, a biasing circuit assembly for an amplifier can include a biasing circuit configured to provide a first bias signal or a second bias signal through a common node and a ballast to an input path of an amplifying transistor for operation in a first mode or a second mode, respectively. The biasing circuit assembly can further include a linearizing circuit implemented to couple the common node and a node along the input path. The linearizing circuit can be configured to improve linearity of the amplifying transistor operating in the first mode while allowing the ballast to be sufficiently robust for the amplifying transistor operating in the second mode.

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. The low noise amplifier includes a first inductor, an amplification circuit, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.