The present disclosure facilitates impedance matching between a power amplifier and filters. A radio-frequency circuit includes a power amplifier, a plurality of transmit filters, a switch, a plurality of first matching networks, and a second matching network. The switch switches the plurality of transmit filters to be coupled to the power amplifier. The plurality of first matching networks are coupled between the plurality of transmit filters and the switch. The second matching network is coupled between the power amplifier and the switch. The second matching network includes a transmission line transformer.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.

A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.

A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.

A semiconductor device package includes a plurality of input leads, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combined output lead configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal.

Provided are an input matching circuit, at least one amplifying transistor that receives a signal from the input matching circuit, a first dummy transistor that receives a signal from the input matching circuit, a second dummy transistor that receives a signal from the input matching circuit, and an output matching circuit that outputs an output of the amplifying transistor, the amplifying transistor being arranged between the first dummy transistor and the second dummy transistor, the amplifying transistor, the first dummy transistor, and the second dummy transistor being provided in a row along the input matching circuit.

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. An overload protection circuit can adjust an impedance of a switch coupled to the low noise amplifier based on a signal level of the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.