A circuit includes a transmitter associated with a carrier of a radio frequency interconnect, a transmission channel communicatively coupled with the transmitter, and a receiver communicatively coupled with the transmission channel, the receiver also being associated with the carrier of the radio frequency interconnect. A combiner on a transmitter-side of the transmission channel is coupled between the transmitter and the transmission channel, and a decoupler on a receiver-side of the transmission channel is coupled between the receiver and the transmission channel. A channel loss compensation circuit is communicatively coupled between the transmitter and the receiver.

To enable a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. A semiconductor device including: a wiring substrate; a semiconductor chip disposed on an upper surface of the wiring substrate so as to direct a bottom surface of the chip to face the upper surface; a resin portion formed between the wiring substrate and the semiconductor chip; and a circuit element embedded in the resin portion, in which the circuit element includes: a first terminal connected to wiring formed on the upper surface of the wiring substrate; and a second terminal connected to a bump provided on a lower surface of the semiconductor chip, and the circuit element is embedded in the resin portion with the first terminal facing the upper surface of the wiring substrate and the second terminal facing the lower surface of the semiconductor chip.

A power amplifier includes a main amplifier, an auxiliary amplifier, and a control circuit. The main amplifier is configured to amplify input power, and the auxiliary amplifier is configured to amplify the input power when the input power exceeds a certain level. The control circuit, which is provided between a source of the main amplifier and a ground, is configured to control a source potential of the main amplifier so as to increase the source potential when the input power reaches at least a certain value.

The embodiments described herein use resonant circuits to provide isolation between closely proximate conductors. For example, these resonant circuits can be used to reduce unwanted electromagnetic coupling and minimize crosstalk energy between package leads, bonding wires, and circuit board traces on radio frequency (RF) electronic devices, including RF power amplifiers. To facilitate a reduction in electromagnetic coupling, the resonant circuit is configured resonate with the closely proximate conductors at a selected frequency f.sub.0, and when resonating at the selected frequency f.sub.0 the resonant circuit provides a path to ground for the crosstalk energy. This path to ground reduces the crosstalk energy that would otherwise be shared between the two closely proximate conductors, and thus provides the electromagnetic isolation between the conductors.

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.

A capacitor includes a body including a substrate having first and second capacitor regions, and first to third terminal electrodes disposed on an external surface of the body. The first capacitor region includes a plurality of first trenches, and a first capacitor layer disposed on one surface of the substrate and in the first trenches in the first capacitor region and including at least one first dielectric layer and first and second electrodes disposed with the at least one first dielectric layer interposed therebetween. The second capacitor region includes a plurality of second trenches, and a second capacitor layer disposed on one surface of the substrate and the second trenches in the second capacitor region and including at least one second dielectric layer and third and fourth electrodes disposed with the at least one second dielectric layer interposed therebetween. The second capacitor layer has a specific surface area greater than that of the first capacitor layer.

A capacitor includes a body including a substrate having first and second capacitor regions, and first to third terminal electrodes disposed on an external surface of the body. The first capacitor region includes a plurality of first trenches, and a first capacitor layer disposed on one surface of the substrate and in the first trenches in the first capacitor region and including at least one first dielectric layer and first and second electrodes disposed with the at least one first dielectric layer interposed therebetween. The second capacitor region includes a plurality of second trenches, and a second capacitor layer disposed on one surface of the substrate and the second trenches in the second capacitor region and including at least one second dielectric layer and third and fourth electrodes disposed with the at least one second dielectric layer interposed therebetween. The second capacitor layer has a specific surface area greater than that of the first capacitor layer.

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die.

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.