A transceiver includes first electrical channels and second electrical channels. The first electrical channels are configured to transfer electromagnetic signals to first air waveguides. Each of the first electrical channels extend from a transmitter along an exterior surface of a chip package that supports the transmitter and terminate at first transitions on the exterior surface. Each of the first plurality of air waveguides are attached to the exterior surface and overlay one of the first transitions. The transceiver also includes second electrical channels configured to transfer second electromagnetic signals from second air waveguides. Each of the second electrical channels extend from a receiver along the exterior surface of the chip package that supports the receiver and terminate at second transitions on the exterior surface. Each of the second air waveguides are attached to the exterior surface and overlay one of the second transitions.

A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

The present invention provides a dual-substrate antenna package structure and a method for manufacturing the same. The package structure includes a main substrate and at least one antenna substrate. The antenna substrate is provided on a pad of the main substrate by an array of solder balls placed on the antenna substrate, at least one chip is electrically connected to the main substrate, and metal wiring provided on the main substrate electrically connects the pad to the chip. The array of solder balls includes support solder balls and conventional solder balls, and the support solder balls have a melting point high than 250° C. A spacing distance between the antenna substrate and the main substrate can be kept stable during the reflow soldering process and subsequent processes because the support solder balls having the high melting point can always maintain the stability of the structure during the reflow soldering process.

A method of manufacturing a semiconductor device, includes: preparing a support substrate having a peeling layer formed on a main surface side; partially forming a wiring layer above the peeling layer; arranging a semiconductor chip on the support substrate so that a pad of the semiconductor chip is electrically connected to the wiring layer; forming an encapsulating layer that encapsulates at least a part of the wiring layer and the semiconductor chip and is in contact with the peeling layer or a layer above the peeling layer so as to form an intermediate laminated body including the semiconductor chip, the wiring layer, and the encapsulating layer on the support substrate; cutting a peripheral portion of the support substrate after forming the intermediate laminated body; and mechanically peeling the intermediate laminated body from the support substrate with the peripheral portion cut away, with the peeling layer being as a boundary.

A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

A device comprises an integrated circuit (IC) die, a substrate, a printed circuit board (PCB), an antenna, and a waveguide stub. The IC die is affixed to the substrate, which comprises a signal launch on a surface of the substrate that is configured to emit or receive a signal. The substrate and the antenna are affixed to the PCB, such that the signal launch and a waveguide opening of the antenna are aligned and comprise a signal channel. The waveguide stub is arranged as a boundary around the signal channel. In some implementations, the waveguide stub has a height of λ/4, where λ represents a wavelength of the signal. In some implementations, the antenna includes the waveguide stub; in others, the substrate includes the waveguide stub.

An amplifier includes a package that includes a carrier amplifier having a carrier amplifier input and output, a peaking amplifier having a peaking amplifier input and output, and corresponding input and output leads. The package includes a first integrated passive device including a first capacitor structure. The first integrated passive device includes a first contact pad coupled to the peaking amplifier output and a second contact pad coupled to the peaking output lead. The package includes a second integrated passive device including a second capacitor structure. The second integrated passive device includes a third contact pad coupled to the carrier amplifier output and a fourth contact pad coupled to the carrier output lead. The amplifier includes input circuitry a combining node configured to combine a carrier output signal and a peaking output signal.

A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.