A wave phased array is manufactured using additive manufacturing technology (AMT). The wave phased array includes a radiator, a radiator dilation layer supporting the radiator, a beamformer supporting the radiator dilation layer, a beamformer dilation layer supporting the beamformer, and a substrate support layer supporting the beamformer dilation layer. At least one of the radiator, the radiator dilation layer, the beamformer, the beamformer dilation layer and the substrate support layer is fabricated at least in part by an AMT process.

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.

An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.

Provided is an electronic device including a substrate, a first metal layer, an electronic component, a cover layer, and an adhesive layer. The first metal layer is formed on the substrate. The electronic component is disposed on the substrate and electrically connected to the first metal layer. The adhesive layer is adhered to the substrate and the cover layer.

In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

What is disclosed is a module arrangement. An antenna device and at least one electronic component are arranged next to each other and within one plane between a top side and a bottom side of the module arrangement. A shielding device which has a shielding effect relative to electromagnetic signals is located between the antenna device and the electronic component. Additionally, a method for manufacturing a module arrangement is disclosed.

A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.