Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 m.

A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.

A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 m.

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 m) and fifty micrometers (50 m) from the lead. In some embodiments, the core covers between at least approximately one-third () and one-half () of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.