A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

The present disclosure relates to a production process for a solder electrode, including a step (1) of forming a coating film of a photosensitive resin composition on a substrate having an electrode pad; a step (2) of forming resist having an opening in a region corresponding to the electrode pad by selectively exposing the coating film to light and further developing the film; a step (3) of heating and/or exposing the resist to light; and a step (4) of filling the opening with molten solder while heating the solder. According to the production process for the solder electrode of the present disclosure, development of cracks on a resist surface can be prevented, and solder filling capability can be improved, even when the resist receives high heat during solder filling as in an IMS method, and therefore the solder electrode adapted for the purpose can be appropriately produced.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

An electronic device includes a semiconductor die having a first side, an orthogonal second side for mounting to a substrate or circuit board, a conductive terminal on the first side, the conductive terminal having a center that is spaced apart from the second side by a first distance along a direction, and a solder structure extending on the conductive terminal, the solder structure having a center that is spaced apart from the center of the conductive terminal by a non-zero second distance along the direction.

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).