A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

A method of transferring micro devices includes: aligning a detachable transfer plate by an alignment assistive mechanism; picking up the micro devices and detaching the detachable transfer plate from the alignment assistive mechanism; placing the detachable transfer plate with the micro devices thereon into a transfer head stocker capable of storing multiple detachable transfer plates; moving the transfer head stocker to a place near an another alignment assistive mechanism; disassembling the detachable transfer plate with the micro devices thereon from the transfer head stocker; moving the detachable transfer plate with the micro devices thereon to be assembled to another alignment assistive mechanism above a receiving substrate to form a device transfer assembly; aligning the micro devices on the detachable transfer plate with the receiving substrate; and transferring the micro devices to the receiving substrate by the another alignment assistive mechanism through the detachable transfer plate.

After a die is picked up with a bond head, a first optical system views and determines a position and orientation of the die relative to the bond head. Separately, a second optical system views and determines a position and orientation of the bonding location when the second optical system has its focal plane configured at a first distance from the second optical system. After the bond head is moved adjacent to the second optical system, the second optical system views and determines a position and orientation of the bond head when the second optical system has its focal plane configured at a second distance from the second optical system. The position and orientation of the die may then be adjusted to correct a relative offset between the die and the bonding location prior to depositing the die onto the bonding location.

An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

A substrate with built-in component includes: a first wiring layer having at least one reference pattern; a first insulating layer formed on the first wiring layer; and an electronic component mounted, in a cavity formed in the first insulating layer, on the first wiring layer, wherein the at least one reference pattern includes at least one first portion crossing a side surface of the electronic component in plan view, and at least one second portion crossing a side surface of the cavity in plan view.

Provided is an assembly jig set of semiconductor module having a plurality of semiconductor chips, the assembly jig set comprising: a first outer frame jig; and a plurality of inner piece jigs positioned by the first outer frame jig and each having a sectioned shape corresponding to the first outer frame jig, wherein one of the inner piece jigs has a plurality of opening portions for positioning the semiconductor chips. A manufacturing method of a semiconductor module using an assembly jig set is provided.

A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.