This invention provides a high-yielding and high-density/ultra-fine pitch package for ultra-large-scale ICs and advanced ICs. The package includes a substrate and a semiconductor chip. The substrate has a passivation layer covering a first surface of the substrate, wherein a plurality of holes are formed in the passivation layer, and a plurality of solder balls respectively accommodated in the plurality of holes. The semiconductor chip has a first plurality of pads, wherein a plurality of copper pillar micro-bumps respectively extend from the first plurality of pads, and the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls.

Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

The present disclosure relates an integrated chip structure. The integrated chip structure includes a first chiplet predominantly having a first plurality of integrated chip devices coupled to a first plurality of interconnects over a first substrate. The first plurality of integrated chip devices are a first type of integrated chip device. The integrated chip structure further includes a second chiplet predominantly having a second plurality of integrated chip devices coupled to a second plurality of interconnects over a second substrate. The second plurality of integrated chip devices are a second type of integrated chip device different than the first type of integrated chip device. One or more inter-chiplet connectors are between the first and second chiplets and are configured to electrically couple the first and second chiplets. The first plurality of interconnects have a first minimum width different than a second minimum width of the second plurality of interconnects.

A bonding structure is provided, including a first substrate; a second substrate disposed opposite the first substrate; a first bonding layer disposed on the first substrate; a second bonding layer disposed on the second substrate and opposite the first bonding layer; and a silver feature disposed between the first bonding layer and the second bonding layer. The silver feature includes a silver nano-twinned structure including parallel twin boundaries. The silver nano-twinned structure includes 90% or more [111] crystal orientation. A method for forming a bonding structure is also provided. Each of steps of forming a first silver feature and second silver feature includes sputtering or evaporation coating. Negative bias ion bombardment is applied to the first silver feature and second silver feature during sputtering or evaporation.

An integrated circuit includes a T-coil formed in a first metal layer, wherein the T-coil may include: a first inductor connected to a first terminal and a second terminal; and a second inductor connected to the second terminal and a third terminal, wherein the first inductor and the second inductor may include a first pattern and a second pattern, respectively, the first and second patterns extending parallel to each other in a first direction from the second terminal in the first metal layer, and wherein the first pattern and the second pattern may form a bridge capacitor of the T-coil.

One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

A semiconductor structure includes a fan-out package, a packaging substrate, an solder material portions bonded to the fan-out package and the packaging substrate, an underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the underfill material portion and having a Young's modulus is lower than a Young's modulus of the underfill material portion.