A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.

A semiconductor package is provided in which a first adhesive film includes a first extension portion extending relative to a side surface of a first semiconductor chip in a second direction, perpendicular to the first direction, the first extension portion has an upper surface including a first recess concave toward a base chip, each of the plurality of second adhesive films includes a second extension portion extending relative to side surfaces of the plurality of second semiconductor chips in the second direction, and the second extension portion has an upper surface including a second recess concave in the first direction and a lower surface including a protrusion in the first recess or the second recess.

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

A chip packaging method and a chip packaging structure is disclosed. The method includes: attaching at least two chips to one side of substrate by adhesive layer, wherein device surface of the chip faces the substrate, and the substrate is provided therein with substrate wiring structure and/or chip; performing thinning treatment on the at least two chips provided on one side of the substrate, wherein the thinning treatment includes etching only the chips to reduce the thickness of the chips; plastically sealing the chips having undergone the thinning treatment to form a plastically sealed arrangement layer, and stacking at least two such plastically sealed arrangement layers on the substrate along plastic sealing direction; and punching the chips having undergone the thinning treatment to form first interconnection hole connecting the chips having undergone the thinning treatment to the substrate wiring structure, the chip in substrate, or the plastically sealed arrangement layer.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate having a plurality of conductive through-glass vias (TGV); a magnetic core inductor including: a first conductive TGV at least partially surrounded by a magnetic material; and a second conductive TGV electrically coupled to the first TGV; a first die in a first dielectric layer, wherein the first dielectric layer is on the glass substrate; and a second die in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the second die is electrically coupled to the magnetic core inductor.

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.

A semiconductor device according to the present embodiment includes a substrate having a first semiconductor circuit provided thereon. First pads are located on the substrate. A first insulating layer is located on an outer side of each of the first pads. Second pads are respectively bonded to the first pads. A second insulating layer is located on an outer side of each of the second pads and is bonded to the first insulating layer. The first pads each include a first conductive material, and a first insulating material located on an inner side of the first conductive material on a bonding surface of the first pads and the second pads.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.