A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.

A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

Electronic modules and methods of fabrication are described. In an embodiment, an electronic module includes a molded system-in-package, and a flexible circuit mounted on a side surface of a molding compound layer such that the flexible circuit is in electrical contact with a lateral interconnect exposed along the side surface of the molding compound layer.

A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

A method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. The first plurality of electrical connectors are laid out as having a honeycomb pattern. A second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.

An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.