A composite integrated circuit (IC) structure includes at least a first IC die in a stack with a second IC die. Each die has a device layer and metallization layers interconnected to transistors of the device layer and terminating at features. First features of the first IC die are primarily of a first composition with a first microstructure. Second features of the second IC die are primarily of a second composition or a second microstructure. A first one of the second features is in direct contact with one of the first features. The second composition has a thermal conductivity at least an order of magnitude lower than that of the first composition and first microstructure. The first composition may have a thermal conductivity at least 40 times that of the second composition or second microstructure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.

IC devices with backend memory and electrical feedthrough networks of interconnects between the opposite sides of the IC devices, and associated assemblies, packages, and methods, are disclosed. An example IC device includes a back-side interconnect structure, comprising back-side interconnects; a frontend layer, comprising frontend transistors; a backend layer, comprising backend memory cells and backend interconnects; and a front-side interconnect structure, comprising front-side interconnects. In such an IC device, the frontend layer is between the back-side interconnect structure and the backend layer, the backend layer is between the frontend layer and the front-side interconnect structure, and at least one of the back-side interconnects is electrically coupled to at least one of the front-side interconnects by an electrical feedthrough network of two or more of the backend interconnects.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the insulating material including a second conductive pathway electrically coupled to the TSV; and a second microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the first microelectronic component.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

Embodiments described herein may be related to apparatuses, processes, and techniques related to a transceiver architecture for inter-die communication on-package using mm-wave/THz interconnects. In particular, amplifier-less transceivers are used in combination with on-package low loss transmission lines to provide inter-die communication. In embodiments, signals on the interconnect may be transmitted between up conversion mixers and down conversion mixers without any additional amplification. Other embodiments may be described and/or claimed.

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.