Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern, wherein the interconnect structure includes a graphene liner. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.

A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.

The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Electrical interconnections may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The electrical interconnections may include conductors in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device, the second semiconductor device and the substrate between the bond pads and the pad of the routing members. An encapsulant distinct from the dielectric material may cover the electrical interconnections, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.