The present application provides a semiconductor package and a manufacturing method for the semiconductor package. The semiconductor package includes a package substrate, a first semiconductor die, a second semiconductor die, a first encapsulant and a second encapsulant. The package substrate has a first side and a second side facing away from the first side, and the second side has a concave recessed from a planar portion of the second side. The first semiconductor die is attached to the first side of the package substrate. The second semiconductor die is attached to a recessed surface of the concave. The first encapsulant covers the first side of the package substrate and encapsulates the first semiconductor die. The second encapsulant fills up the concave and encapsulates the second semiconductor die.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

Embodiments disclosed herein include chiplet modules and die modules. In an embodiment, a chiplet module comprises a first chiplet, where the first chiplet comprises a first active surface. In an embodiment the chiplet module further comprises a second chiplet, where the second chiplet comprises a second active surface. In an embodiment, the chiplet module further comprises a hybrid bonding interface between the first chiplet and the second chiplet, where the hybrid bonding interface electrically couples the first chiplet to the second chiplet.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.