In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

A semiconductor package includes a substrate, a die stack on the substrate, and connection terminals between the substrate and the die stack. The die stack includes a first die having a first active surface facing the substrate, the first die including first through electrodes vertically penetrating the first die, a second die on the first die and having a second active surface, the second die including second through electrodes vertically penetrating the second die, and a third die on the second die and having a third active surface facing the substrate. The second active surface of the second die is in direct contact with one of the first or third active surfaces.

An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate.

The disclosure provides a power supply module, including: a pin; a magnetic core including: a first and second magnetic plate arranged in parallel; a first upper wiring layer; a first middle wiring layer; a first lower wiring layer, wherein at least a part of the first upper wiring layer and the first middle wiring layer are connected to form a first winding surrounding the first magnetic plate, at least a part of the first lower wiring layer and the first middle wiring layer are connected to form a second winding surrounding the second magnetic plate. The magnetic core, the first and second winding form a magnetic element electrically connected to a switch. A magnetic loop surrounds a first axis, the first winding surrounds a second axis, the second winding surrounds a third axis, the first, second and third axis are parallel to a plane where the pin is located.

A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

A composite structure includes a first metal layer, a second metal layer, and a ceramic layer disposed therebetween. The ceramic layer has a first surface and a second surface opposite to each other and is adapted to absorb electromagnetic waves. The absorbance reaction range of the electromagnetic waves by the ceramic layer ranges from 100 MHz to 400 GHz. The first metal layer has an opening exposing the second surface. An inner sidewall of the first metal layer surrounds the opening. The orthographic projection of the second metal layer on the ceramic layer at least partially overlaps the orthographic projection of the opening on the ceramic layer. The thickness ratio of the first metal layer to the second metal layer is 1:1 to 1:2. The area ratio of the first metal layer to the second metal layer is 1:1.2 to 1:4. A package architecture including the composite structure is also provided.

A semiconductor device and semiconductor package, the device including a lower semiconductor chip including a lower through-electrode; an interposer mounted on the lower semiconductor chip, the interposer including an interposer substrate; a plurality of interposer through-electrodes penetrating through at least a portion of the interposer substrate in a vertical direction and electrically connected to the lower through-electrode; and at least one capacitor in the interposer substrate and electrically connected to at least one interposer through-electrode of the plurality of interposer through-electrodes; and an upper semiconductor chip mounted on the interposer and electrically connected to the interposer through-electrode.