According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

Semiconductor device assemblies having stacked semiconductor dies and electrically functional heat transfer structures (HTSs) are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a mounting surface with a base region and a peripheral region adjacent the base region. At least one second semiconductor die can be electrically coupled to the first semiconductor die at the base region. The device assembly can also include an HTS electrically coupled to the first semiconductor die at the peripheral region.

A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.

A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

A method for forming a thermal conduction structure includes: a substrate is provided, at least a dielectric layer being formed on the substrate; a Through Silicon Via (TSV) and at least one silicon blind hole are formed, where the at least one silicon blind hole is located on at least one side of the TSV, the TSV penetrates through the substrate and the dielectric layer, and each silicon blind hole does not penetrate through the substrate.