A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A package substrate includes; a conductive line extending in a first horizontal direction, a conductive pad on an upper surface of the package substrate and horizontally spaced apart from the conductive line in a second horizontal direction, and a protective layer covering the conductive line and including an opening selectively exposing a portion of the conductive pad. The opening has an elongated elliptical shape having a minor axis defined by a width extending in the first horizontal direction and a major axis defined by a length extending in the second horizontal direction.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.

A semiconductor package including a redistribution substrate extending in a first direction and a second direction perpendicular to the first direction, a semiconductor chip mounted on a top surface of the redistribution substrate, and an outer terminal on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, a redistribution insulating layer covering a top surface and a side surface of the under-bump pattern, a protection pattern interposed between the top surface of the under-bump pattern and the redistribution insulating layer, and interposed between the side surface of the under-bump pattern and the redistribution insulating layer, and a redistribution pattern on the under-bump pattern. The outer terminal may be disposed on a bottom surface of the under-bump pattern.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

A semiconductor package includes a redistribution substrate having a first redistribution layer, a semiconductor chip on the redistribution substrate and connected to the first redistribution layer, a vertical connection conductor on the redistribution substrate and electrically connected to the semiconductor chip through the first redistribution layer, a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor, and an encapsulant covering at least a portion of each of the semiconductor chip, the vertical connection conductor, and the core member, the encapsulant filling the first and second through-holes, wherein the vertical connection conductor has a cross-sectional shape with a side surface tapered to have a width of a lower surface thereof is narrower than a width of an upper surface thereof, and the first and second through-holes have a cross-sectional shape tapered in a direction opposite to the vertical connection conductor.

A semiconductor package includes a semiconductor chip including a connecting pad, a mold layer covering the semiconductor chip, a lower redistribution layer on the semiconductor chip and the mold layer, and a connecting terminal on the lower redistribution layer. The lower redistribution layer includes a first lower insulating layer, a first conformal redistribution pattern extending through the first lower insulating layer, a second lower insulating layer on the first lower insulating layer and the first conformal redistribution pattern, and a first filled redistribution pattern disposed on the first conformal redistribution pattern and extending through the second lower insulating layer. A side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the first conformal redistribution pattern. The second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.

Exemplary package on package (PoP) assemblies may include a substrate. The PoP assemblies may include a first package positioned on a first side of the substrate with a bottom surface of the first package facing the substrate. The PoP assemblies may include a second package positioned on a second side of the substrate with a top surface of the second package facing the substrate. The second side may be positioned opposite the first side. The PoP assemblies may include a conductive element that contacts one or both of a top surface and the bottom surface of the second package and extends to a position that is aligned with or above a top surface of the first package.