A method of manufacturing an electronic package is provided, in which a package module including a routing structure is stacked on a carrier structure via a plurality of conductive elements, a heat dissipation member covers a part of a surface of the routing structure, and an electronic module is disposed on another part of the surface of the routing structure, so that the routing structure is formed with at least one heat dissipation pad bonded to the heat dissipation member, such that the heat energy of the electronic module and the package module can be dissipated via the heat dissipation pad and the heat dissipation member.

A semiconductor package includes a first sub-semiconductor package, an interposer substrate, and a second sub-semiconductor package that are sequentially stacked. The first sub-semiconductor package includes a first package substrate, a first semiconductor device, and a first mold member that are sequentially stacked, and the interposer substrate includes at least one hole. The first mold member includes: a mold main portion which covers the first semiconductor device; a mold connecting portion extended from the mold main portion and inserted into the at least one hole; and a mold protruding portion extended from the mold connecting portion to cover a top surface of the interposer substrate outside the at least one hole. The mold main portion, the mold connecting portion, and the mold protruding portion constitute a single object.

A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate. The semiconductor package additionally includes connection terminals disposed between the lower and upper package substrates. The connection terminals comprise outermost connection terminals and inner connection terminals. The inner connection terminals are disposed between the lower semiconductor chip and outermost connection terminals. The semiconductor package further includes a first under-fill layer disposed between the lower package substrate and the upper package substrate. At least one of the outermost connection terminals is disposed outside of the lower mold layer.

A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface which face each other, an alignment pattern formed on the first surface, a first redistribution layer arranged on the first surface of the first semiconductor chip, a second redistribution layer arranged on the second surface of the first semiconductor chip, and electrically connected with the semiconductor chip, and a first dielectric layer including the alignment pattern between the first redistribution layer and the semiconductor chip, the alignment pattern overlapping the first surface of the first semiconductor chip.

A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.

An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.