A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

Provided is a semiconductor package. The semiconductor package may include a substrate, a semiconductor chip on the substrate, a passive element on the substrate, a conductive structure on the substrate, and an interposer substrate on the semiconductor chip, the passive element, and the conductive structure. The interposer substrate may be electrically connected to the conductive structure. A height of the passive element may be greater than a height of the semiconductor chip.

A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

An example of a printable electronic component includes a component substrate having a connection post side and an opposing contact pad side. The component can include one or more non-planar, electrically conductive connection posts protruding from the connection post side of the component substrate. Each of the one or more connection posts can have a peak area smaller than a base area. The component can include one or more non-planar, electrically conductive exposed component contact pads disposed on (e.g., directly on, indirectly on, or in) the contact pad side of the component substrate. Multiple components can be stacked such that connection post(s) of one are in contact with non-planar contact(s) of one or more others.

A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip arranged on the first substrate, a first group of at least one solder ball arranged on a side surface of the first semiconductor chip, an interposer arranged on the first semiconductor chip and the first substrate and being in contact with the first group of at least one solder ball, and an adhesive layer arranged between the first semiconductor chip and the interposer and configured to expose at least a portion of un upper surface of the first semiconductor chip, wherein a first height from an upper surface of the first substrate to the upper surface of the first semiconductor chip is greater than a second height of the first group of at least one solder ball.

An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die,

a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

A printable electronic component includes a component substrate and a circuit disposed in or on the component substrate. One or more electrically conductive connection posts protrude from the component substrate. One or more electrically conductive component contact pads are exposed on or over the component substrate on a side of the component substrate opposite the one or more connection posts. The one or more component contact pads and the one or more electrically conductive connection posts are both electrically connected to the circuit. The components can be printed onto a destination substrate and electrically connected to contact pads on the destination substrate through the connection posts. The components can also be printed onto other components and electrically connected through the connection posts and component contact pads to form a three-dimensional electronic structure.