An electro-optic device may include a substrate layer, and a first photonic layer over the substrate layer and having a first photonic device. The electro-optic device may include a second photonic layer over the first photonic layer and having a second photonic device. The electro-optic device may include a dielectric layer over the second photonic layer, and a first electrically conductive via extending through the dielectric layer and the second photonic layer to couple to the first photonic device, and a second electrically conductive via extending through the dielectric layer and coupling to the second photonic device. The electro-optic device may include a third electrically conductive via extending through the substrate layer, the second photonic layer, and the first photonic layer to couple to the substrate layer.

A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

A method of cleaning post-etch residues on a copper line includes providing a copper line which is divided into a first region and a second region. A dielectric layer is formed on the copper line. After that, the dielectric layer is etched to form openings in the dielectric layer. A number of openings within the first region is more than a number of openings in the second region. During the etching process, a potential difference is formed between the first region and the second region of the copper line. Finally, the dielectric layer and the copper line are cleaned by a solution with a PH value. The PH value has a special relation with the potential difference.

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.

Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed.

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a first reservoir in a surface layer on the first contact surface and a second reservoir in a surface layer on the second contact surface, the surface layers of the first and second contact surfaces being comprised of respective native oxide materials of one or more second educts respectively contained in reaction layers of the first and second substrates, partially filling the first and second reservoirs with one or more first educts; and reacting the first educts filled in the first reservoir with the second educts contained in the reaction layer of the second substrate to at least partially strengthen a permanent bond formed between the first and second contact surfaces.

A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member.