A fluid sampler includes: a sample cell that includes: a substrate comprising: a first port; a second port in fluid communication with the first port; a viewing reservoir in fluid communication with the first port and the second port and that receives the fluid from the first port and communicates the fluid to the second port, the viewing reservoir including : a first view membrane; a second view membrane; and a pillar interposed between the first view membrane and second view membrane, the pillar separating the first view membrane from the second view membrane at a substantially constant separation distance such that a volume of the viewing reservoir is substantially constant and invariable with respect to a temperature and invariable with respect to a pressure to which the sample cell is subjected.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

Some implementations herein include a semiconductor die and methods of formation. The semiconductor die includes an array of interconnect pad structures, including interconnect pad structures having surfaces located within an overlay region of an active device area of the semiconductor die. As part of manufacturing the semiconductor die, temporary conductive structures are formed across the overlay region to support wafer acceptance testing and/or circuit probe testing process. Forming the temporary conductive structures includes using an anti-reflective coating layer having a composition that enables the temporary conductive structures to be formed using a single etch cycle. Relative to other semiconductor dies manufactured using temporary conductive structures formed using an anti-reflective coating layer having another composition (and that may require multiple etch cycles), the semiconductor die includes a reduced difference in step heights between interconnect pad structures in the overlay region and other regions of the active device area.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.