A semiconductor module according to the present disclosure includes a first substrate having a plurality of patterns having two or more different thickness, a first semiconductor device disposed on at least one or more patterns, a second substrate having a plurality of patterns having two or more different thickness. One or more of the plurality of patterns of the second substrate is placed on the first semiconductor device, a first terminal pattern and a second terminal pattern, each disposed between the first substrate and the second substrate, the first terminal pattern comprises a first upper terminal pattern and a first lower terminal pattern, and the second terminal pattern comprises a second upper terminal pattern and a second lower terminal pattern, and a conductive frame coupled to at least one of the first and the second terminal patterns.

A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.

A medical apparatus includes a power device, a temperature sensor, a conversion processing unit and a prediction time period calculation unit. The temperature sensor detects temperature data. The conversion processing unit refers to temperature data obtained by the temperature sensor in a table in which at least one of temperature data for inside a case covering the power device and temperature data for a wire bonded to the power device is associated with data of actually measured temperatures, and obtains at least one of the temperature data for inside the case and the temperature data for the wire. The prediction time period calculation unit calculates a prediction time period until a failure of the power device based on the obtained temperature data.

There is provided a semiconductor device 1 which comprises: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing; a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5; a plurality of pressure means 40 for applying pressure to the plurality of semiconductor units 30, respectively, wherein the plurality of pressure means 40 are arranged between the plurality of semiconductor units 30 and the first housing electrode 5; a first conductive structure 14 arranged between the plurality of pressure means 40 and the plurality of semiconductor units 30, wherein the plurality of semiconductor units 30 are electrically connected in parallel between the second housing electrode 4 and the first conductive structure 14; and a second conductive structure 18 configured to provide a current flow path from the first conductive structure 14 to the first housing electrode 5, the second conductive structure comprising a first part 16 that is fixedly connected to the first conductive structure 14 and a second part 9 that is fixedly connected to the first housing electrode 5.

Provided is a semiconductor device having a wiring structure on a semiconductor element and capable of securing high quality and high reliability in response to the desire for high-temperature operations, a large-current specification, thinner wafers, smaller device size, and reduced loss. A semiconductor device that includes an insulating circuit board; a semiconductor element implemented on the insulating circuit board; a first insulating resin layer laminated on the insulating circuit board; a copper-plated wiring which contacts the semiconductor element via a window portion formed in the first insulating resin layer, which enables contact with the semiconductor element; and a second insulating resin layer laminated so as to seal the copper-plated wiring, and a method for producing the semiconductor device are provided.

A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.