An electronic package is provided. The electronic package comprises a substrate having a first region and a second region; a first set of electronic components mounted on the substrate in the first region; a second set of electronic components mounted on the substrate in the second region; an encapsulant layer disposed on the substrate and encapsulating the first and second sets of electronic components; a set of interconnect components disposed on the substrate in the second region, and extending through the encapsulant layer, wherein the set of interconnect components are electrically coupled to the first and second sets of electronic components; and a connector mounted on the encapsulant layer and electrically coupled to the first and second sets of electronic components through the set of interconnect components.

A packaged integrated circuit includes a core structure with a cavity therein; a component accommodated in the cavity; an electrically insulating structure formed over the core structure and the component; a partially electrically insulating carrier structure formed below the core structure and the component; and an electrically conducting redistribution arrangement formed at least partially within the carrier structure. The redistribution arrangement includes conductor structures each having a first element extending through the carrier structure and electrically connecting a contact of the component and a second element below the carrier structure. A part of the second element is a contact pad for electrically connecting the redistribution arrangement with external circuitry. The carrier structure includes a polyimide layer and an adhesive layer. The adhesive layer is directly attached to an upper surface of the polyimide layer and to a lower surface of the core structure and a lower surface of the component.

A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

A printed wiring board includes conductor layers, a core layer having an opening, and a build-up layer. A high frequency device placed within the opening is installed such that a mirror surface is thermally connected to a conductor layer for heat dissipation facing the opening from a lower surface side of the core layer, and terminals on the terminal surface are electrically connected to conductor layers formed on an upper surface side of the core layer.

A method of manufacturing a component-embedded substrate includes a resist forming step in which a patterning resist is formed on a support, a patterning step in which a through hole extending through the resist is formed by performing patterning on the resist, a first-electrode forming step in which a through-via electrode is formed by filling the through hole with an electrode material, a resist removing step in which the resist is removed, a component placement step in which an electronic component is placed, a substrate forming step in which a resin substrate is formed by sealing the electronic component with a resin that includes a filler having a diameter larger than the surface roughness of a side surface of the through-via electrode, and a removing step in which the support is removed from the resin substrate. The first-electrode forming step is performed before the substrate forming step is performed.

A method for manufacturing a semiconductor component including: providing a flat carrier with an upper side and a lower side, the carrier including a continuous opening that runs between the upper side and the lower side; providing a semiconductor arrangement that includes a semiconductor chip that includes electrically and/or optically active regions on a lower side; arranging the semiconductor arrangement in the opening such that a lower side of the semiconductor arrangement and the lower side of the carrier run in a common plane; casting the semiconductor arrangement with a potting compound, such that the semiconductor arrangement is materially connected to the carrier; and thinning out the semiconductor system by way of grinding from above, such that an upper side of the carrier and an upper side of the semiconductor arrangement run in a common plane.

It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.

In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.

A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack disposed on the first surface of the carrier substrate. The chip stack includes a first semiconductor die, a second semiconductor die, and an interposer between the first semiconductor die and the second semiconductor die. The interposer transmits signals between the first semiconductor die and the second semiconductor die.