Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.

Packaged RF transistor amplifiers are provided that include a flat no-lead overmold package that includes a die pad, a plurality of terminal pads and an overmold encapsulation that at least partially covers the die pad and the terminal pads and an RF transistor amplifier die mounted on the die pad and at least partially covered by the overmold encapsulation. These packaged RF transistor amplifiers may have an output power density of at least 3.0 W/mm.sup.2.

A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

A component comprises at least one support on which is fixed at least one electronic circuit, for example a circuit of MMIC type, one or more layers of organic materials stacked on the support according to a technique of printed circuit type and forming a pre-existing cavity containing the electronic circuit, the cavity being filled with a material of low permeability to water vapor such as LCP.

An electronic device includes a first electronic component including a first signal line and a first ground conductor surface, a second electronic component that is placed above the first electronic component and includes a second signal line and a second ground conductor surface opposed to the first ground conductor surface, a waveguide including the first ground conductor surface, the second ground conductor surface, and a pair of first ground conductor walls that are opposed to each other and are placed between the first ground conductor surface and the second ground conductor surface, a first transducing part that transduces a signal between the first signal line and the waveguide, and a second transducing part that transduces a signal between the second signal line and the waveguide.

An electronic device includes a first electronic component including a first signal line and a first ground conductor surface, a second electronic component that is placed above the first electronic component and includes a second signal line and a second ground conductor surface opposed to the first ground conductor surface, a waveguide including the first ground conductor surface, the second ground conductor surface, and a pair of first ground conductor walls that are opposed to each other and are placed between the first ground conductor surface and the second ground conductor surface, a first transducing part that transduces a signal between the first signal line and the waveguide, and a second transducing part that transduces a signal between the second signal line and the waveguide.

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.

A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed.

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.