An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.

An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.

According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.

A display according to various embodiments may include: a first face oriented in a first direction; a second face oriented in a second direction opposite the first direction; a plurality of pixels disposed in a space between the first face and the second face; and a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device. Each of the plurality of pixels may include a plurality of LEDs and a driving circuit. A conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit may be located in the space and a wiring line configured to electrically connect the driving circuit to the plurality of pins may be located in the space.

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.

A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die.

A semiconductor package includes a leadframe having a clip foot portion, the clip foot portion having a first tie bar, a conductive clip situated over the leadframe, the conductive clip including a first lock fork having at least two prongs around the first tie bar so as to secure the conductive clip to the clip foot portion of the leadframe. The conductive clip includes a second lock fork having at least two prongs around a second tie bar of the clip foot portion. The conductive clip is electrically coupled to the clip foot portion of the leadframe. The clip foot portion of the leadframe includes exposed leads. The semiconductor package also includes at least one semiconductor device situated on the leadframe. The at least one semiconductor device is coupled to a driver integrated circuit situated on the leadframe.

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel.

According to an aspect, a display device includes: a substrate including a display region and a non-display region surrounding the display region; at least one driver IC including connecting terminals with a first surface fixed to face the non-display region; first wires supplying a signal to the display region; first bumps connected with the first wires; second wires transferring a signal to and from outside; second bumps connected with the second wires; and inspection wires. The connecting terminals of the driver IC include first connecting terminals overlapping the first or second bumps in plan view, and second connecting terminals not overlapping the first or second bumps in plan view. The inspection wires include a connecting conductor between themselves and at least one of the second connecting terminals. The inspection wires are pulled out to an outside of the driver IC in plan view.