A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.

A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

An electronic component includes a first set comprising an interconnect layer and an electronic circuit having a front face and a back face, which is connected to the interconnect layer by the front face, wherein the first set comprises a metal plate having a front face and a back face joined to the back face of the electronic circuit; a coupling agent between the front face of the metal plate and the back face of the electronic circuit, configured to thermally and electrically connect the metal plate to the electronic circuit; and in that the electronic component comprises: one or more layers made of organic materials stacked around the first set and the metal plate using a printed circuit-type technique and encapsulating the electronic circuit; a thermally conductive metal surface arranged at least partially in contact with the back face of the metal plate.

A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.