Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed over the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core portion and a shell portion, the shell portion surrounding all side ails of the core portion, and wherein the shell portion has a higher melting point than the core portion.

A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other. In forming the stacked substrate, in a state where the fourth main surface is bonded to the third main surface, a fifth main surface of the third substrate opposite to the fourth main surface is thinned.