Patent classifications
H01L2924/15159
Rod-based substrate with ringed interconnect layers
An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.
ELECTRONIC CIRCUIT MODULE
An electronic circuit module includes a circuit board, electronic components, an embedding layer, and a conductive film. The circuit board has a first principal surface, a second principal surface and a side surface, and includes a pattern conductor and a via conductor. The conductive film is connected to a conduction path to a ground electrode. The side surface includes a first region, a second region having a longer circumferential length than the first region, and a connection region connecting the first region and the second regions. The conductive film is formed on a region including at least part of each of an outer surface of the embedding layer, the first region, and the connection region. The conductive film formed on at least part of the connection region is connected to an exposed portion in the connection region of the via conductor included in the conduction path to the ground electrode.
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate
Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
Substrate design for semiconductor packages and method of forming same
An embodiment device package includes a package substrate and a first and a second die bonded to the package substrate. The package substrate includes a build-up portion comprising a first contact pad and a plurality of bump pads. The package substrate further includes an organic core attached to the build-up portion, a through-via electrically connected to the first contact pad and extending through the organic core, a second contact pad on the through-via, a connector on the second contact pad, and a cavity extending through the organic core. The cavity exposes the plurality of bump pads, and the first die is disposed on the cavity and is bonded to the plurality of bump pads.
Stacked semiconductor packages with cantilever pads
One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.
Methods and devices for fabricating and assembling printable semiconductor elements
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE
A manufacturing method of a semiconductor package which improves productivity and can manufacture high-quality semiconductor packages is provided. The manufacturing method of a semiconductor package includes arranging a plurality of semiconductor devices at intervals on a first surface side of a support substrate, forming a first insulating resin layer forming wiring connected to each of the plurality of semiconductor devices and embeds the plurality of semiconductor devices, cutting from the first surface side in areas between the plurality of semiconductor devices, forming a first groove portion penetrating the first insulating resin layer and exposing the support substrate, and dividing individual semiconductor packages by forming a resist pattern having openings arranged corresponding to the first groove portion on a second surface on the opposite side of the first surface, etching the openings from the second surface side, and forming a second groove portion on the second surface side
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.
SLOPED INTERCONNECTOR FOR STACKED DIE PACKAGE
A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.
SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.