The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.

A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

A semiconductor package structure includes a substrate. The substrate includes a first ground layer. The first ground layer has a body and a first tooth protruding from a side of the body. The first tooth has a first lateral side. The first lateral side of the first tooth is inclined relative to the side of the body in a top view of the first ground layer.

A multi-piece wiring substrate includes a matrix substrate including a first main surface, a second main surface opposite to the first main surface, a third main surface disposed between the first main surface and the second main surface, an arrangement of a plurality of wiring substrate regions, a margin region surrounding the plurality of wiring substrate regions, and a dividing groove. The multi-piece wiring substrate further includes a through-hole disposed across the boundary between the wiring substrate regions or the boundary between the wiring substrate regions and the margin region, and which penetrates from the first main surface to the second main surface, and an external connection conductor at each corner of the wiring substrate regions on the second main surface. An auxiliary conductor is disposed around the through-hole on the third main surface.

A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.

A ball grid array (BGA) package for an integrated circuit device includes an integrated circuit device having a plurality of terminals, and two largest dimensions that define a major plane. A package substrate material encloses the integrated circuit device, and is formed, in a plane parallel to the major plane, into a polygon having at least five sides. An array of contacts on an exterior surface of the package substrate material is electrically coupled to the plurality of terminals. Contacts in the array of contacts are distributed in a pattern of contact positions, and the center of each contact position may be separated from the center of each nearest other position by a separation distance that is identical throughout the pattern. Each position may be occupied by a contact, or positions in a sub-pattern may lack a contact and may be available for insertion of at least one via.

Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.