A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, and a third LED sub-unit disposed on the second LED sub-unit, in which the third LED sub-unit is configured to emit light having a shorter wavelength than that of light emitted from the first LED sub-unit, and to emit light having a longer wavelength than that of light emitted from the second LED sub-unit.

There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

A high-frequency component includes a resin layer and a high-frequency circuit provided in and on the resin layer and includes an inductor and an electronic component. The electronic component is arranged on an upper surface of the resin layer. The inductor includes first and second metal pins provided such that upper end surfaces thereof are exposed from the upper surface of the resin layer and lower end surfaces thereof are exposed from a lower surface of the resin layer. The electronic component has a first outer electrode provided at a position superposed with the upper end surface of the first metal pin in plan view and is connected to the first metal pin, and a second outer electrode provided at a position superposed with the upper end surface of the second metal pin in plan view and is connected to the second metal pin.

A display device including a film substrate including first and second surfaces, the first surface being opposite to the second surface; a semiconductor chip disposed on the first surface and including an input terminal and a test terminal, which are arranged in a first direction; a first wire extending from the input terminal on the first surface along a second direction, which intersects the first direction; and a second wire including a first extended portion, which extends along the first surface, a second extended portion, which extends along the second surface, and a first via, which penetrates the film substrate and connects the first extended portion and the second extended portion, wherein the first extended portion extends from the test terminal in the second direction and is connected to the first via, and the second extended portion extends from the first via to an edge of the second surface.

This thermocompression bonding device is provided with a heating tool (1) and a backup member (3). The backup member (3) has: a support portion (3a) which faces the tip (1a) of the heating tool (1) while first and second members (111, 122) to be joined and a cushioning member (2) are located therebetween, and which supports the first and second members (111, 122) to be joined; and a body portion (3b) provided on the opposite side of the support portion (3a) from the first and second members (111, 122) to be joined. The support portion (3a) is formed so that the heat conductivity thereof is lower than that of the body portion (3b).

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

Disclosed herein is a chip-on-film including: a base film; a driver mounted on one of upper and lower surfaces of the base film; and at least one pad group, which includes signal wiring lines disposed on the upper and lower surfaces of the base film and transmitting signals via two paths, a first pad and a second pad disposed on one of the upper and lower surfaces of the base film, and a plurality of through-holes disposed between the first pad and the second pad and electrically connecting the signal wiring lines to each other, wherein the first pad and the second pad are separated a predetermined distance from each other in a width direction of the base film, and each of the first pad and the second pad is obliquely arranged in plural in a longitudinal direction of the base film.

An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

A chip connection method and structure are provided. The method includes: providing a first connection line and a second connection line on a substrate, wherein, in the thickness direction of the substrate, a distance between the first connection line and the chip is smaller than a distance between the second connection line and the chip; providing the chip on a top surface of the substrate, the chip being provided with at least two chip pins; and providing the substrate with a second through hole corresponding to the second connecting line and provided therein with a second conductive layer, at least one chip pin being electrically connected to the first connection line, and at least one of the remaining chip pin being corresponding to a first opening of the second through, and the second conductive layer electrically connecting the chip pin and the second connection line.