An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

A radio-frequency module includes a module substrate, a power amplifier, and a control circuit configured to control the power amplifier. The control circuit includes a temperature sensor. The power amplifier and the control circuit are stacked one on top of another on a principal surface of the module substrate.

A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

A semiconductor package includes a lower redistribution layer, a lower semiconductor chip and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip has an active plane corresponding to an active plane of the lower semiconductor chip and is disposed on the upper redistribution layer. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first substrate. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through electrode fills a through hole extending from the second surface toward the first surface.

Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.

A method for manufacturing a semiconductor package includes forming a pad pattern including a metal film on a semiconductor chip; forming an insulating layer covering the pad pattern and including an organic insulating material; and forming an opening exposing a surface of the metal film of the pad pattern by performing laser processing on the insulating layer, wherein, in forming the opening, a region to be plastically deformed on the metal film by the laser processing is formed.

An imaging element according to the present disclosure is an imaging element flip-chip mounted on a wiring substrate, in which a projection is provided on a side surface of the imaging element such that a bottom surface side of the imaging element projects from a top surface side. Then, in the imaging device according to the present disclosure, the imaging device is flip-chip mounted on the wiring substrate so that a top surface of the imaging element faces the wiring substrate, and an outer periphery of the imaging element on the wiring substrate is sealed with a sealing material. An adhesion site of the sealing material is urged to a side of the projection, so that penetration of a solute and a solvent forming the sealing material may be reduced.

A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.