An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.

The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.

The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.

A semiconductor device suitable for preventing malfunction is provided.

The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.