A semiconductor package including a first substrate including a first bump pad and a filling compensation film (FCF) around the first bump pad; a second substrate facing the first substrate and including a second bump pad; a bump structure (BS) in contact with the first bump pad and the second bump pad; and a non-conductive film (NCF) surrounding the BS and between the first substrate and the second substrate, wherein the NCF covers an upper surface and an edge of the FCF.

A semiconductor device includes: a substrate on which wiring is formed; a first semiconductor element flip-chip bonded to the substrate; a second semiconductor element provided on the first semiconductor element; a first resin provided in at least part of a region between the first semiconductor element and the substrate; a second resin provided in at least part of a region between the second semiconductor element and the substrate; and a member having a thermal conductivity higher than a thermal conductivity of the first resin and a thermal conductivity of the second resin, provided between the first resin and the second resin, having a part overlapping with an upper surface of the first semiconductor element, and having another part overlapping with a first wiring part as part of the wiring in a top view.

A semiconductor device includes: a substrate on which wiring is formed; a first semiconductor element flip-chip bonded to the substrate; a second semiconductor element provided on the first semiconductor element; a first resin provided in at least part of a region between the first semiconductor element and the substrate; a second resin provided in at least part of a region between the second semiconductor element and the substrate; and a member having a thermal conductivity higher than a thermal conductivity of the first resin and a thermal conductivity of the second resin, provided between the first resin and the second resin, having a part overlapping with an upper surface of the first semiconductor element, and having another part overlapping with a first wiring part as part of the wiring in a top view.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.

A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

A package comprising a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and a second solder resist layer coupled to the second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.

According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.