A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Provided is a semiconductor package. The semiconductor package comprises a semiconductor chip on a substrate, a voltage measurement circuit configured to measure an external voltage to be input into the semiconductor chip and a thermoelectric module configured to convert heat released from the semiconductor chip into an auxiliary power, and configured to apply the auxiliary power to the semiconductor chip, the thermoelectric module being separated from the voltage measurement circuit, wherein the voltage measurement circuit is configured to control the thermoelectric module to apply the auxiliary power to the semiconductor chip in response to a change in the external voltage.

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.