A semiconductor device has a shielding layer over a semiconductor package. A plurality of slot lines define a location to form a slot in the shielding layer. The slot is formed in the shielding layer by cutting along the slot lines with a laser controlled by a scanner to read the slot lines. The slot lines include a left boundary slot line and right boundary slot line. The slot can be cut in the shielding layer by performing an edge cut along the slot lines, and performing a peel back to form the slot in the shielding layer. Alternatively, the slot can be cut in the shielding layer by performing a first cut in a first direction along the slot lines, and performing a second cut in a second direction opposite the first direction along the slot lines to form the slot in the shielding layer.

An antenna module includes a base member, an antenna that includes a radiating element disposed in or on the base member, first and second feed lines each of which is connected to the radiating element, and a control circuit that is connected to the radiating element via the first feed line and the second feed line. The control circuit includes a signal processing circuit that is connected to the antenna via the first feed line and the second feed line and an antenna inspection circuit that checks an electrical conductivity of an electrical conduction path connecting the first feed line, the radiating element, and the second feed line to one another.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.

A method of manufacturing an electronic package is disclosed. The described method includes (a) placing an electronic component on at least one layer structure; (b) encapsulating the electronic component by an encapsulant in a pressureless way; and (c) forming at least one further layer structure at the layer structure to thereby form a stack beneath the encapsulated electronic component. A further described electronic package includes (a) a stack comprising at least one layer structure and at least one further layer structure; (b) an electronic component being placed on the stack; and (c) an encapsulant encapsulating the electronic component, wherein the encapsulant has been formed in a pressureless way. Further described is an electronic device comprising such an electronic package.

A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

An electronic device includes a carrier having at least one bonding pad, a plurality of electronic elements disposed on the carrier and one of the electronic elements including a substrate and at least one connecting terminal disposed between the substrate and the carrier. The electronic elements are electrically connected to the at least one bonding pad via the at least one connecting terminal.

Disclosed herein are antenna boards, integrated circuit (IC) packages, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an IC package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.

An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.