A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

In one example, a semiconductor device, includes a substrate having a substrate top side, a substrate bottom side, a substrate dielectric structure, and a substrate conductive structure. The substrate conductive structure includes a transceiver pattern proximate to a substrate top side. An antenna structure includes an antenna dielectric structure coupled to the substrate top side, an antenna conductive structure having an antenna element, and a cavity below the antenna element. The antenna element overlies the transceiver pattern. The cavity includes a cavity ceiling, a cavity base, and a cavity sidewall between the cavity ceiling and the cavity base. Either a bottom surface of the antenna element defines the cavity ceiling and a perimeter portion of the antenna element is fixed to the antenna dielectric structure, or the antenna dielectric structure includes a body portion having a bottom surface that defines the cavity ceiling and the antenna element is vertically spaced apart from the bottom surface of the body portion. An semiconductor component is coupled to a bottom side of the substrate and is coupled to the transceiver pattern. Other examples and related methods are also disclosed herein.

A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

A semiconductor package is provided. The semiconductor package includes a redistribution layer, a semiconductor chip, solder balls, an interposer, an encapsulant layer, and an underfill layer. The semiconductor chip is electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer. The solder balls are disposed on the upper surface of the redistribution layer spaced apart from the semiconductor chip and are electrically connected to the redistribution layer. The interposer is electrically connected to the solder balls, and is disposed on an upper surface of the solder balls. The encapsulant layer encapsulates the semiconductor chip and side surfaces of the redistribution layer under the interposer. The underfill layer fills a space between a lower surface of the interposer and an upper surface of the encapsulant layer. The encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer.

A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.

Aspects of this disclosure relate to methods of radio frequency signal processing. A radio frequency signal is received at an antenna on a first side of a multi-layer substrate and a low noise amplifier is disposed on a second side of the multi-layer substrate such that a ground plane of the multi-layer substrate is positioned between the antenna and the low noise amplifier. The radio frequency signal is provided to and amplified by the low noise amplifier.

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.