A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.

Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.

The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.

A module includes a substrate including a first surface, at least one first component mounted on the first surface, a shield member mounted on the first surface to cover the first component, and a first sealing resin arranged at least between the shield member and the first surface. The shield member includes a top surface portion in a form of a plate and a plurality of leg portions that extend from the top surface portion toward the first surface.

A method includes forming a layer stack with at least one electrically insulating layer structure and at least one patterned electrically conductive layer structure on a temporary carrier, the layer stack includes a lower surface adjoining the temporary carrier and an upper surface opposite to the lower surface; mounting a first component at the upper surface; placing a first frame structure at the upper surface, the first frame structure surrounding at least partially the first component; covering the first component with a first coating material, the first coating material spatially extending at least partially into voids at or within the first frame structure and into voids at or within the layer stack; and removing the temporary carrier. The lower surface of the layer stack is an even surface. The opposite upper surface of the layer stack is an uneven surface. An electronic package can be manufactured with the described method.

A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.

A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A thermal conductive structure including a die pad portion is affixed to the semiconductor die. A limb portion of the thermal conductive structure extends laterally away from the die pad portion and overlaps a portion of the package substrate. A thermal conduction path is formed between the semiconductor die and a distal end of the limb portion.

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.